1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a multi-chip package for implementing two or more semiconductor chips of different sizes and functions with one package.
2. Description of the Prior Art
In the semiconductor industry, the packaging technique for IC chips is continuously progressing. In particular, with the recent development of the information and communication industry, efforts have been continuously made to develop small, light and multifunctional packages. As a result of such efforts, a so-called “multi-chip package” has been proposed.
Such a multi-chip package is to increase memory capacity by stacking memory chips of a same size and function or to maximize the performance and efficiency of products by assembling various kinds of semiconductor chips of different sizes and functions. For example, two or more DRAMs are stacked to realize a high capacity, and a SRAM, a flash memory, an RF chip, etc. are simultaneously packaged and applied to a small and light portable communication device or the like.
There are many types of multi-chip packages according to their end-use products, makers, etc. Two typical examples of multi-chip packages according to the prior art are shown in FIGS. 1 and 2.
The conventional multi-chip package 10 shown in FIG. 1 is a type of thin small outline package (TSOP), in which individual packages 11, 12 are stacked. Whereas, the conventional multi-chip package shown in FIG. 2 is a type of ball grid array (BGA), in which individual semiconductor chips 21, 22, 23 are vertically stacked or horizontally arranged and then collectively packaged.
In the multi-chip package 10 shown in FIG. 10, the individual packages 11,12 each comprise one semiconductor chip 10 and employ a lead-on-chip (LOC) lead frame. One or more internal leads 14 of the lead frame are adhered to the top surface of the semiconductor chip 13 by an adhesive tape and each electrically connected to the semiconductor chip 13 by a gold wire 16. The upper and lower stacked packages 11 and 12 are electrically interconnected by means of one or more separate connection leads 17. Herein, the connection leads 17 are bonded to one or more external leads 18 of each lead frame and serve as external connection terminals.
The multi-chip package 20 forms a single package, in which semiconductor chips 21, 22 and 23 are vertically stacked or horizontally arranged on one side of a printed circuit substrate 24. An adhesive 25 provides physical adhesion between the semiconductor chip 21 and the semiconductor chip 21 or between the semiconductor chips 21 and 22 and the semiconductor chip 23 and gold wires 26 provide electrical connection therebetween. The other side of the circuit substrate 24 is provided with solder balls that serve as external connection terminals.
The conventional multi-chip packages as described above have various disadvantages to be described below.
The multi-chip package 10 shown in FIG. 1 has a disadvantage in that its total height is increased because it is a package-stacked type. Therefore, it is difficult to apply the multi-chip package 10 of this type to a portable communication device. Furthermore, the chips 13 employed in the multi-chip package 10 must have a same size. If the chips 13 are of different sizes, the connection parts between the individual packages 11, 12 and/or between the external leads 18 and the interconnection leads 17 may be fractured due to a package warping phenomenon caused by the difference of thermal expansion coefficients thereof.
The multi-chip package 20 has a limit in vertically stacking the semiconductor chips 21, 22, 23. In this regard, if the semiconductor chips 21, 22, 23 are horizontally arranged, a problem arises in that the area of the multi-chip package 20 is increased. In addition, if memory chips of a same type are employed to increase the memory capacity, there will be a problem in that it is difficult to stack the chips as a result of the memory chips being same in size.
Meanwhile, the multi-chip packages shown in FIGS. 1 and 2 have a common problem in that they are not suitable for the products of high-speed devices because gold wires 16, 26 are used as electrical connection means.